[antlr-interest] Re: AST generation
Loring Craymer
Loring.G.Craymer at jpl.nasa.gov
Mon Feb 14 14:57:10 PST 2005
You can setType() and setText() on any node. That's usually the easy solution.
--Loring
At 01:24 PM 2/14/2005, Tak-po Li wrote:
>An example of module in Verilog looks as following:
>
>Module (A, B, C);
> .
> .
> .
>endmodule;
>
>
>I am using the following to generate the AST tree for the above:
>
>list_of_ports
> : (LPAREN^ name_of_port (COMMA! name_of_port)* RPAREN!)?
> ;
>module : "module"^ name_of_module list_of_ports SEMI!
> (module_item)*
> "endmodule"!
> ;
>
>AST tree is generated correctly. However, one of the node is "(" which is
>generated by LPAREN^ statement. Could I change "(" to something else in
>AST generation that I would have less problem in AST tree walk later?
>
>
>I am new to Antlr. Could someone help? Thanks.
>
>
>Tak
>
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