[antlr-interest] Problem with Tree grammar

[naveed riaz]

I am using the following tree grammar ,
class VerilogParser extends Parser;
options{
k = 2;                        // two token lookahead
exportVocab = Verilog;
defaultErrorHandler = false;
buildAST = true;       // Call its vocabulary
"Verilog"
}
tokens{
MODULE_NAME;}

source_text :
        ( description )*
    EOF!
        ;

description :
        module
            ;

module options {defaultErrorHandler = true;} :
        p:"module"^ {#p.setType(MODULE_NAME);} 
         name_of_module   ( list_of_ports )? SEMI!
    "endmodule"!
        ;

list_of_ports :
        LPAREN! port ( COMMA^ port )* RPAREN!
        ;

port :
    (port_expression)?
 |
        DOT! name_of_port LPAREN! (port_expression)?
RPAREN!
    ;

port_expression :
        port_reference |
    LBRACE! port_reference ( COMMA^ port_reference )*
RBRACE!
        ;
port_reference :
        ( name_of_variable LBRACK expression COLON )
=>
        name_of_variable LBRACK! expression! COLON!
expression! RBRACK |
        ( name_of_variable LBRACK ) =>
        name_of_variable LBRACK! expression RBRACK |
        name_of_variable
    ;
expression: (|)
;
name_of_module :            local_identifier ;
name_of_port   :             local_identifier;
name_of_variable: local_identifier ;
local_identifier :
        IDENTIFIER
        ;


When i give the input 
module d_ff ( d, clk, q, q_bar);
The parser works fine but it does not show any tree
structure.....Whats the cause???whats faulty in grammar..


 




		
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