[antlr-interest] FW: Thanks for Your Help and question

james_cataldo at agilent.com james_cataldo at agilent.com
Mon Jul 31 08:56:57 PDT 2006


Naveed,
 
I'm forwarding this onto the list, in case anyone else has an opinion.

________________________________

From: Naveed Riaz [mailto:nriaz at ist.tugraz.at] 
Sent: Monday, July 31, 2006 8:54 AM
To: james_cataldo at agilent.com
Subject: Re: Thanks for Your Help and question


 I am mailing you this time for two problems i am facing... I shall be really grateful if you spare a part of your
precious time and kindly mention the causes of the problems i am facing...

I am using the following tree grammar , 
class VerilogParser extends Parser;
options{
k = 2;                        // two token lookahead
exportVocab = Verilog;
defaultErrorHandler = false; 
buildAST = true;       // Call its vocabulary "Verilog"
}
tokens{
MODULE_NAME;}

source_text :
        ( description )*
    EOF!
        ;

description :
        module
            ;

module options {defaultErrorHandler = true;} :
        p:"module"^ {#p.setType(MODULE_NAME);}  
         name_of_module   ( list_of_ports )? SEMI!
    "endmodule"!
        ;

list_of_ports :
        LPAREN! port ( COMMA^ port )* RPAREN!
        ;

port :
    (port_expression)?
 |
        DOT! name_of_port LPAREN! (port_expression)? RPAREN!
    ;

port_expression :
        port_reference |
    LBRACE! port_reference ( COMMA^ port_reference )* RBRACE!
        ;
port_reference :
        ( name_of_variable LBRACK expression COLON ) =>
        name_of_variable LBRACK! expression! COLON! expression! RBRACK |
        ( name_of_variable LBRACK ) =>
        name_of_variable LBRACK! expression RBRACK |
        name_of_variable
    ;
expression: (|)
;
name_of_module :            local_identifier ;
name_of_port   :             local_identifier;
name_of_variable: local_identifier ;
local_identifier :
        IDENTIFIER 
        ;


When i give the input  
module d_ff ( d, clk, q, q_bar);
The parser works fine but it does not show any tree structure.....Whats the cause???whats faulty in grammar..
i want it to be showed like "module" as the parent and then its name and the list of ports as children and further
the individual ports as children of list of ports....


The other problem i why it gives me error if i want to change the above grammar to the following grammar,
i have used (**) sign for the problem part.
source_text :
        ( description )*
    EOF!
        ;

description :
        module
            ;

module  :
        "module"         name_of_module^(**)   ( list_of_ports )? SEMI!
    "endmodule"!
        ;

list_of_ports :
        LPAREN! port^(**) ( COMMA port )* RPAREN!
        ;

port :
    (port_expression)?
 |
        DOT! name_of_port^(**) LPAREN! (port_expression)? RPAREN!
    ;

port_expression :
        port_reference |
    LBRACE! port_reference(**) ( COMMA port_reference )* RBRACE!
        ;
port_reference :
        ( name_of_variable LBRACK expression COLON ) =>
        name_of_variable^(**) LBRACK! expression! COLON! expression! RBRACK |
        ( name_of_variable LBRACK ) =>
        name_of_variable LBRACK! expression RBRACK |
        name_of_variable
    ;
expression: (|)
;
name_of_module :            local_identifier ;
name_of_port   :             local_identifier;
name_of_variable: local_identifier ;
local_identifier :
        IDENTIFIER 
        ;






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