[antlr-interest] escaped identifier in Verilog

[Tak-po Li]

There is so called "escape identifier" in Verilog as: \cciTimer[0]
Where "ccTimer" is the normal identifier.  "[0]" is the vector (or array expansion).  There is no white character between '\' and 'c'.
 
I recall the Verilog example in antlr.org for v2 handles it as:
 
ESCAPED_IDENTIFIER     : '\\'! (~ '\040')+ ('\040'|'\t'|'\n')!    ;
 
It seems it is not working for v3.  Could anyone help with a solution for v3?
 
Thanks,
 
Tak
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