[antlr-interest] escaped identifier in Verilog

[Gavin Lambert]

At 05:34 14/12/2007, Tak-po Li wrote:
>I recall the Verilog example in antlr.org for v2 handles it as:
>
>ESCAPED_IDENTIFIER
>     : '\\'! (~ '\040')+ ('\040'|'\t'|'\n')!
>     ;

First off, try changing the '\040's into ' 's.  I'm not sure if v3 
supports octal escapes.