[antlr-interest] nested parsing (BSDL)

[Harald M. Müller]

I admit I only scanned your email: But the "textbook approach", in my
opinion would be the following:

1. Have a VHDL parser, which accepts strings simply as strings.
2. Do an AST rewrite, where you do "constant folding", i.e. you compute
expressions that are made up only of constants. This will at least
concatenate the &-separated strings.
3. Do another AST rewrite where you interpret the strings by calling another
lexer+parser on them, return an AST from them and put that AST into the
already existing AST structure.

Another possibility would be to try to define a "LONG_STRING" symbol in the
VHDL lexer, which allows string constants with & and comments to be passed
to the lexer as a simple string; thus, you could get rid of stage 2. above;
and maybe it is then possible to call the nested parsers of step 3.
immediately while parsing, so that you end up with a 1-pass machine (but I
would definitely keep the multiple grammars apart).
This possibility will not allow constructs with parentheses like

constant DW_PACKAGE:PIN_MAP_STRING:="CLK:1, Q:(2,3,4,5,7,8,9,10), " &
           ( "D:(23,22,21,20,19,17,16,15),"  &
             ( "GND:6, VCC:18, OC_NEG:24, TDO:11, TMS:12, TCK:13, TDI:14" )
           );

which might be allowed in the syntax of VHDL. Also, with constant folding
you could maybe tackle beasts like

   constant B0 = "00000000";
   constant B1 = "00000001";
   constant B2 = "00000010";
   constant B3 = "00000011";
   ...
   constant T0 = "10000000";
   constant T1 = "10000001";
   ...

   attribute INSTRUCTION_OPCODE of ttl74bct8374 : entity is
        "BYPASS (11111111, 10001000, 00000101, 10000100, 00000001),"   &
        "EXTEST (" & B0 & ", " & T0 & "," &
        "SAMPLE (" & B2 & ", " & T2 & "," &
   ...

or something like that where one starts to use constants in the "nested
program."

When I find a little time, I might look once more into this ...