[antlr-interest] Vhdl and Verilog grammars problem

Mamado mamado+groups at gmail.com
Tue Nov 25 05:25:34 PST 2008


Hello All,

I was trying to create a common tree parser for Vhdl and Verilog, and I was
glad to find both grammars available on ANTLR.

I installed ANTLRWorks and opened the Vhdl and Verilog grammars to try to
generate code, but I got errors in both of them.

[15:23:09] error(208): vhdl.g:1633:1: The following token definitions can
never be matched because prior tokens match the same input:
BASE,BASE_SPECIFIER,LETTER,HEXDIGIT,INTEGER,DIGIT

I am new to ANTLR, though I know a bit about BNF and Parser/Lexer, I tried
to look at the grammar file but didn't understand why this error happens.

I assumed that the grammar files posted on the site should work out of the
box, so I think I am doing something wrong, or there is some settings I
need.

Can someone please help me.

Thanks a lot,
Mamado.
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