[antlr-interest] VHDL Target

Bart Kiers bkiers at gmail.com
Mon Apr 26 22:50:16 PDT 2010


>
>
>
>  On Mon, Apr 26, 2010 at 10:02 PM, David Blubaugh <
> davidblubaugh2000 at yahoo.com<http://us.mc1133.mail.yahoo.com/mc/compose?to=davidblubaugh2000@yahoo.com>
> > wrote:
>
>> To All,
>>
>> Has anyone developed a VHDL target within ANTLR??
>
>
> Hi, do you really mean a VHDL-target (being able to generate VHDL
> sourcefiles from a given grammar?), or did you mean a VHDL-grammar?
>
> Regards,
>
> Bart.
>
>
> >
> Both
>
> Thank You
>
> David


The examples section has a couple of VHDL grammars:
http://www.antlr.org/grammar/list

I'm not familiar with the language itself, but I doubt there is a VHDL
target around (if even possible since it is some sort of of
hardware-modeling language). Why do you need a VHDL-target? What problem are
you trying to solve? Some more info cuold clarify things.

Bart.


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