[antlr-interest] estimate about creating a parser

[Free HDL]

Loring Craymer <craymer at ...> writes:

> 
> This is one of those cases where you should be looking to borrow rather than
> build, given the time constraints.  Google "VHDL ANTLR" and you will get a
> number of useful hits, including the VHDL parser posted on antlr.org
> (http://www.antlr.org/grammar/1086696923011/vhdlams/index.html).
> 
> --Loring
> 
> > -----Original Message-----
> > From: antlr-interest-bounces at ... [mailto:antlr-interest-
> > bounces at ...] On Behalf Of Sohail Somani
> > Sent: Monday, May 01, 2006 9:44 AM
> > To: duboimat at ...
> > Cc: antlr-interest at ...
> > Subject: Re: [antlr-interest] estimate about creating a parser
> > 
> > On Mon, 2006-05-01 at 12:14 -0400, duboimat at ... wrote:
> > > We would like to create a VHDL parser (with AST).
> > >
> > > Is it possible to create this parser in one month?
> > 
> > Its possible if you know antlr+VHDL well enough.
> 
> 


Hi,
   You can visit the Free EAD tool site-
http://www.questatechnologies.com
to download free tools/utlities around VHDL/Verilog.
I am listing some of these free utilities here-
  1) Verilog Netlist parser
  2) SoC builder, IP integration tool
  3) VHDL, Verilog testbench generator
  4) Intuitive VHDL/Verilog/Mixed sorting for proper analysis alongwith
     proper working library
  5) Design hierarchy bowser and module dependency browser
  6) VHDL2IPXACT, Verilog2VhdlEntity converter

All these are free utlities and you can get enhancement/customization
free of cost just by sending your requirement details. Prpmpt support
is there .

Thanks.