[stringtemplate-interest] outline assignment symbols

[Philippe Faes]

Dear stringtemplate users,

In the VHDL language, many users like to outline assingments so that  
the assignment symbols line up, like this:

foo    := 1;
a      := 2;
foobar := 3;

Is it possible/feasible/easy to generate code like this with  
stringtemplate?

thanks

Philippe

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