[antlr-interest] Re: AST generation

[Tak-po Li]

An example of module in Verilog looks as following:

Module (A, B, C);
     .
     .
     .
endmodule;


I am using the following to generate the AST tree for the above:

list_of_ports
	: (LPAREN^ name_of_port (COMMA! name_of_port)* RPAREN!)?
	;
module  : "module"^ name_of_module  list_of_ports SEMI!
		(module_item)*
		"endmodule"!
	;

AST tree is generated correctly.  However, one of the node is "(" which is 
generated by LPAREN^ statement.  Could I change "(" to something else in AST 
generation that I would have less problem in AST tree walk later?


I am new to Antlr.  Could someone help?  Thanks.


Tak