[antlr-interest] Help Needed Verilog AST

[james_cataldo at agilent.com]

In the options sections of VerilogParser, add 

> buildAST = true; 

This will put the parser in AST generation mode.  The default AST is probably not what you want, but the ANTLR documentation chapter about Tree Parsers should tell you everything you need to know about how to customize it.  The ASTFrame class can help you debug the AST to make sure you get what you want.  I hope this helps.

Adam

-----Original Message-----
From: antlr-interest-bounces at antlr.org [mailto:antlr-interest-bounces at antlr.org] On Behalf Of naveed riaz
Sent: Wednesday, July 26, 2006 7:44 AM
To: antlr-interest at antlr.org
Subject: [antlr-interest] Help Needed Verilog AST

Hi all..
Currently i am working on Verilog diagonosis.
on antlr website there is a grammar available for verilog but i dont think it supports AST.
Is there some one who has worked on Verilog AST or can some one guide me how to change that grammar in such a way that i can get an AST. Any help ......
Best of Regards..


 




		
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