[antlr-interest] escaped identifier in Verilog
Tak-po Li
takpoli at hotmail.com
Fri Dec 14 16:09:58 PST 2007
Thanks, Gavin, I change it as you suggested. It helps passing the compiling. I will report more when I obtain the final result.
Tak
> Date: Fri, 14 Dec 2007 07:21:16 +1300> To: takpoli at hotmail.com; antlr-interest at antlr.org> From: antlr at mirality.co.nz> Subject: Re: [antlr-interest] escaped identifier in Verilog> > At 05:34 14/12/2007, Tak-po Li wrote:> >I recall the Verilog example in antlr.org for v2 handles it as:> >> >ESCAPED_IDENTIFIER> > : '\\'! (~ '\040')+ ('\040'|'\t'|'\n')!> > ;> > First off, try changing the '\040's into ' 's. I'm not sure if v3 > supports octal escapes. >
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