[antlr-interest] About My Verilog HDL grammar

[sunao furukawa]

Hello!

I write Verilog HDL grammar.
I referred http://www.externsoft.ch/download/verilog.html .
I debugging this grammar.
But,primary does not select suitable alternative.
Antlrworks emit NoViableAltException(0@[null]).

Input Text:

module adder4(in_data1, in_data2, out_data, cy);
    input  [3:0] in_data1, in_data2;
    output [3:0] out_data;
    output       cy;

    wire   [4:0] rslt;

    assign rslt     = in_data1 + in_data2;
    assign cy       = rslt[4];
    assign out_data = rslt[3:0];

endmodule

Red letter is emitted at [4] in rslt[4] and at [3:0] in rslt[3:0}.

Syntax primary,below,

primary :  number
 | identifier
 | identifier'[' expression ']'
 | identifier'[' msb_constant_expression ':' lsb_constant_expression ']'
 | concatenation
 | multiple_concatenation
 | function_call
 | '(' mintypmax_expression ')'
 ;

I want to select "identifier'['expression']'" or "identifier'[' 
msb_constant_expression ':' lsb_constant_expression ']'".
But Antlrworks select "identifier".

I will attach my Verilog HDL grammar file.
Start Symbol (source_text).
I don't know what to do.
Help me please.

Thanks.
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